Intel Changes CPU Road Map

Some chips killed, others delayed to ensure compatible configurations.

Tom Krazit, IDG News Service
Tuesday, October 25, 2005
Intel has announced several changes to its road map for server processors, delaying its first dual-core Itanium 2 processor and replacing a future multicore Xeon processor with a new design that eliminates the performance penalty of shared connections to a chipset.

Montecito, the dual-core version of the Itanium 2 processor, will not be available in large volumes until the middle of next year, instead of the early part of next year as originally planned, said Scott McLaughlin, an Intel spokesperson, on Monday. While preliminary shipments of the processor are already under way, Intel decided to make a few changes to the chip in order to reach the company's standard for "production level quality," McLaughlin said, declining to specify the nature of the changes.

But Montecito will no longer ship with Foxton, a sophisticated power-management technology, and the speed of its front-side bus connection to memory will run at 533MHz instead of the 667MHz speed originally scheduled for the design, he said.

Chips Killed
Intel also has killed Whitefield, a multicore Xeon processor for servers with four or more processors, McLaughlin said. It is being replaced by a new processor code-named Tigerton that will appear in 2007, the same time-frame in which Whitefield was expected to arrive.

Tigerton processors will use a high-speed interconnect technology that will allow each processor to connect directly to the server's chipset, McLaughlin said. Current Xeon processors in multiprocessor servers must share a front-side bus connection to the chipset in order to access data from system memory or I/O, a bottleneck that industry analysts have blamed for the current performance gap between Intel's server chips and Advanced Micro Devices Inc.'s Opteron processors.

http://www.pcworld.com/news/article/0,aid,123190,00.asp